RAMBUS

RAMBUS
RAMBUS DRAM is a next-generation DRAM that, instead of taking the features of
standard SDRAM and evolving one or two of them, takes DRAM technology and
rethinks from the ground up how it should be integrated into a system. The DRAM
arrays of memory cells that are at the core of all DRAM types are still there in
RDRAM, but the way that a RDRAM-based system accesses those cells is very
different. These changes in the way that DRAM cells are organized and accessed are
the product of a series of design decisions (many of which were made almost a
decade ago) that are aimed not only at providing the high bandwidth that nextgeneration media applications require but also at solving the granularity and pin
count problems that RAMBUS, Inc. expected to accompany rising transistor counts.
Assuming that pricing considerations aren't an issue (and with RDRAM they often
are), the decision on whether or not to use RDRAM in a system is and should be
made based on the actual bandwidth requirements of the system in question and
whether or not the granularity and pin count problems that RDRAM tries to solve are
actually relevant for that system. And when I say "system," I mean the hardware as
well as OS and application software.
Since we've spent quite a bit of time so far talking about SDRAM's banks, we'll kick
off our examination of RAMBUS with banks as well. Once we talk about the banks
that are the primary organizational unit of RDRAM's core DRAM memory array, we'll
work our way outwards, piece by piece, until we've covered all the relevant parts of
the RDRAM
chip.

Note: I'll be basing this discussion off of a 256/288Mbit (32MB) Direct RDRAM
organized as 512k x 16/18 x 32s. We'll talk about what those last few numbers
mean shortly.

RDRAM Banks
One of RDRAM's claims to fame is that each individual RDRAM chip can hold up to 32
banks of memory. And these banks are individual and self-contained, too--not
spread out among multiple chips like SDRAM banks. Check out this diagram for a
view of RDRAM's core.

1

Each of those banks that go right down the middle of the core holds 1MB, making
this a 32MB chip. Each bank is just a DRAM array that's organized as 512 rows of
128 "dualocts." (A dualoct is just a fancy name for the smallest unit of memory that